1. Field of the Invention
The present invention relates to an address decoder, and especially to an address decoder for a semiconductor memory device of the synchronous type, and which includes a latching circuit for latching an address signal in response to a predetermined clock signal, and a decoding circuit for the latched address signal.
2. Description of the Related Art
Conventionally, a synchronous type static RAM (synchronous type SRAM) in which priority is given to a number of transistors, is constituted as shown by FIG. 5.
In FIG. 5, address signals S and S' are latched by a latching circuit (Latch) 100 in synchronism with a clock signal T. A group U of signals which are output signals from the latching circuit 100, are decoded by decoding circuits (decoder) 110 and the clock signal T is transmitted to NAND circuits (NAND gates) 110a of the decoders 110 to prevent "multiword".
In this case, when the clock signal T arrives at the NAND gates 110a of the decoders 110 before the address signals S and S' arrive at the NAND gates 110a of the decoders 110, "multiword" is caused. Therefore, generally, the NAND gate 110a of the decoder 110 must be supplied the clock signal T which is delayed through the delaying circuit 120.
In this case, the "multiword" signifies that a plurality of WORD lines are simultaneously selected and a selected state of the WORD lines are at "High" level.
Accordingly, as a normal memory constitution, the multiword is prevented by constructing a logic design in which only one of a total of the WORD lines is brought into the "High" level.
As shown by FIG. 6, WORD lines V, W, X and Y are connected to transfer gates 130a through 160a which is connected respectively memory cell 130 through 160.
In this case, when the memory cell 130 stores "High" level and the memory cell 160 stores "Low" level, and the WORD line V and Y cause the multiword, the "High" level of the memory cell 130 and the "Low" level of the memory cell 160 collide with each other and as a result, stored data of either of them is broken.
Accordingly, in the synchronous type SRAM, the multiword is a phenomenon which must never be caused and some measure of avoiding the multiword is needed.
Next, conventionally, in designing a synchronous type SRAM in which priority is given to the characteristic, there has been used a constitution shown by FIG. 7 disclosed in Japanese Laid-Open Patent Application No. 9-265782.
According to a decoder 200 having latch function, a decoder unit 210 and a latch unit 220 are integrally constituted, and the decoder unit 210 is constituted by an NAND gate 210a and an inverter 210b.
In the meantime, the latch unit 220 is constituted of a first group of transmission gates 220a and 220b and a second group of transmission gates 220c and 220d.
The respective groups of transmission gates 220a through 220d comprise PMOSs and NMOSs and are controlled to ON/OFF by supplying outside clocks to gates thereof.
Thereby, two stages of inverters used for inside address signals are reduced, inside address signals are constituted by high-speed formation, a setup margin for an inner clock is secured and high frequency operation is made possible.
The following problems are posed according to the conventional address decoder, mentioned above.
In the case of the former, a time period from when an address signal is set to when data is outputted, is dependent on a delay time period of the delay gate 120. Because the clock signal T is retarded by the delay gate 120 to when the address signals S and S' arrive at the NAND gates 110a of the decoders 110.
Further, in setting the delay time period at the delay gate 120, the delay time needs to be set to include a margin to some degree. Consequently, although the number of transistors are restrained to be small, the time period from when the address signals are set to when the data is outputted is increased. That is, the frequency of the clock signal T is restrained and accordingly, high speed formation of the synchronous SRAM is hindered.
In the meantime, in the case of the latter, although the high speed formation of the synchronous type SRAM can be realized. However, since the decoder unit and the latch unit 220 are integrated and accordingly, the larger a storage capacity, the mores an overhead of an area is produced. That is, the number of transistors is increased.
Further, when power supply is turned on, there is a case in which a plurality of outputs of the NAND gates 210a are selected to be brought into the "High" state. In the worst case, there is a concern in which large current flows until the clock is changed to thereby be broken transistors. Consequently, an initializing circuit needs to provide at an output portion of the NAND gate 210a. This also results in an increase in the number of transistors.
Accordingly, the design can only be carried out by giving priority to either of the number of transistors and the characteristic and it has been very difficult to reduce the number of transistors without being accompanied by a deterioration in the characteristic.